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X80010, X80011, X80012, X80013
Data Sheet January 13, 2005 FN8149.0
PRELIMINARY
Penta-Power Sequence Controller with Hot swap and System Management
The X80010, X80011, X80012, X80013 contain three major functions: a power sequencing controller, a hotswap controller, and systems management support. The power sequencer controller time sequences up to five DC/DC modules. The device allows various DC/DC power sequencing configurations, either parallel or relay modes. The power good, enable, and voltage good signals provide for flexible DC/DC timing configurations. Each voltage enable signal has a built-in delay while additional delay can be added with simple external passive components. The hot swap controller allows a board to be safely inserted and removed from a live backplane without turning off the main power supply. The X80010 family of devices offers a modular, power distribution approach by providing flexibility to solve the hotswap and power sequencing issues for insertion, operations, and extraction. Hardshort Detection and Retry with Delay, Noise filtering, Insertion Overcurrent Bypass, and Gate Current selection are some of the integrated features of the device. During insertion, the gate of an external power MOSFET is clamped low to suppress contact bounce. The undervoltage/overvoltage circuits and the power on reset circuitry suppress the gate turn on until the mechanical bounce has ended. The X80010 turns on the gate with a user set slew rate to limit the inrush current and incorporates an electronic circuit breaker set by a sense resistor. After the load is successfully charged, the PWRGD signal is asserted; indicating that the device is ready to power sequence the DC/DC power bricks. Systems management function provides a reset signal indicating that the power good and all the voltage good signals are active. The reset signal is asserted after a wait state delay. This signal is used to coordinate the hotswap and DC/DC module latencies during power up to avoid "power hang up". In addition, the CPU host can initiate soft insertion or DC voltage module re-sequencing.
Features
* Integrates Three Major Functions - Power Sequencing - Hot Swap Controller - System Management Functions * Penta-Power Sequencing - Sequence up to 5 DC/DC converters. - Four independent voltage enable pins - Four time delay circuits - Soft Power Sequencing - MRC pin restarts sequence without power cycling. * Hot Swap Controller - Programmable overvoltage and undervoltage protection - Undervoltage lockout for battery/redundant supplies - Electronic circuit breaker - Overcurrent Detection and Gate Shut-off - Overcurrent limit during Insertion - Hardshort retry with retry failure flag - Selectable gate current using IGQ pins (10, 70, 150A) - MRH pin controls board insertion/extraction. - Typically operates from -30V to -80V. Tolerates transients to -200V (limited by external components) * System Management - Reset output, with delay, holds off host until all supplies are good - Host control of reinsertion with MRH input - Host control of resequencing using MRC input * Available packages - 32-lead Quad No-Lead Frame (QFN)
Applications
* -48V Hot Swap Power Backplane/Distribution Central Office, Ethernet for VOIP * Card Insertion Detection * Power Sequencing DC/DC/Power Bricks * IP Phone Applications * Databus Power Interfacing * Custom Industrial Power Backplanes * Distributed Power Systems
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X80010, X80011, X80012, X80013 Pinout
QFN package (Top view)
MRH IGQ0 IGQ1 PWRGD BATT-ON FAR NC VEE 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25
VRGO NA1 V4GOOD EN4 V3GOOD EN3 V2GOOD EN2
24 23 22 21 20 19 18 17
(7mm x 7mm)
NC MRC NA1 RESET V1GOOD EN1 NA2 NA2
9 10 11 12 13 14 15 16
VUV/OV
Ordering Information
ORDER NUMBER X80010Q32I X80011Q32I X80012Q32I X80013Q32I OV (V) 74.9 68.0 74.9 68.0 UV1 (V) 42.4 42.4 42.4 42.4 UV2 (V) 33.2 33.2 33.2 33.2 tNF (us) 5 5 5 5 VOC (mV) 50 50 50 50 VOCI (mV) 150 150 150 150 RETRY OVER CURRENT DELAY IGATE (ms) RETRY (A) Always Always 5 retries 5 retries 100 100 100 100 50 50 50 50 TDELAY (ms) 100 100 100 100 tPOR (ms) 100 100 100 100 TEMP RANGE (C) -40 to 85 -40 to 85 -40 to 85 -40 to 85 PART MARK 80010I 80011I 80012I 80013I
Typical Application
BackPlane DC/DC Module 1
ON/OFF
SENSE GATE DRAIN NA1 NA1
VDD
VEE
X80010, X80011, X80012, X80013
DC/DC Module 2
ON/OFF
DC/DC Module 3
ON/OFF
DC/DC Module 4
ON/OFF
-48V RTN R5 30k 1% R4 182k 1% VUV/OV OV=71V UV=37V VDD R6 10k 1%
PWRGD V1GOOD V2GOOD V3GOOD V1 V2 EN1 EN2 EN3 V3
VEE SENSE GATE DRAIN 12V -48V
0.02 5%
4.7V
Rs
0.1uF
100
4.7K 3.3n
100K
V4
Q1 IRFR120
2
FN8149.0 January 13, 2005
X80010, X80011, X80012, X80013
Absolute Maximum Ratings
Temperature under bias . . . . . . . . . . . . . . . . . . . . . -65C to +135C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Voltage on given pin (Hot Side Functions): Vov/uv pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + VEE SENSE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mV + VEE VEE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -80V DRAIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48V + VEE PWRGD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V + VEE GATE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD + VEE FAR pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V + VEE MRH pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + VEE BATT_ON pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + VEE Voltage on given pin (Cold Side Functions): ENi pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ViGOOD pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + VEE RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + VEE MRC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + VEE IGQ1 and IGQ0 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V + VEE VDD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V + VEE D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300C
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40C to 85C Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Electrical Specifications
SYMBOL DC CHARACTERISTICS VDD IDD VRGO IRGO IGATE
(Standard Settings)
TEST CONDITIONS MIN TYP MAX UNIT
Over the recommended operating conditions unless otherwise specified. PARAMETER
Supply Operating Range Supply Current Regulated 5V output VRGO current output Gate Pin Current Gate Drive On, VGATE = VEE, VSENSE = VEE (sourcing) VGATE - VEE = 3V VSENSE-VEE = 0.1V (sinking) IRGO = 10A
10
12 2.5
14 5 6.0 50
V mA
4.5
A A
46.2
52.5
58.8
9 VDD-1 0.9 VEE + 4 1 VDD 1.1 VEE + 5 VEE + 2
mA V V V V A A
VGATE VPGA VIHB VILB ILI ILO
External Gate Drive (Slew Rate Control) Power Good Threshold (PWRGD High to Low) Voltage Input High (BATT_ON) Voltage Input Low (BATT_ON) Input Leakage Current (MRH, MRC) Output Leakage Current (V1GOOD, V2GOOD, V3GOOD, V4GOOD, RESET) Input LOW Voltage (MRH, MRC, IGQ0, IGQ1) Input HIGH Voltage (MRH, MRC, IGQ0, IGQ1)
IGATE = 50A Referenced to VEE VUV1 < VUV/OV < VOV
VIL = GND to VCC All ENi = VRGO for i = 1 to 4
10 10
VIL(3) VIH(3)
-0.5 + VEE (VEE + 5) x 0.7
(VEE + 5) x 0.3 (VEE + 5) + 0.5
V V
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FN8149.0 January 13, 2005
X80010, X80011, X80012, X80013
Electrical Specifications
SYMBOL VOL
(Standard Settings)
TEST CONDITIONS IOL = 4.0mA (VEE + 2.7 to VEE + 5.5V) IOL = 2.0mA (VEE + 2.7 to VEE + 3.6V) VOUT = 0V MIN TYP MAX VEE + 0.4 UNIT V
Over the recommended operating conditions unless otherwise specified. (Continued) PARAMETER Output LOW Voltage (RESET, RESET, V1GOOD, V2GOOD, V3GOOD, V4GOOD, FAR, PWRGD) Output Capacitance (RESET, V1GOOD, V2GOOD, V3GOOD, V4GOOD, FAR) Input Capacitance (MRH, MRC) Over-current threshold Over-current threshold (Insertion)
COUT(1)
8
pF
CIN(1) VOC VOCI
VIN = 0V VOC = VSENSE - VEE VOC = VSENSE - VEE PWRGD = HIGH Initial Power Up condition 45 135 50 150
6 55 165
pF mV mV
VOVR
Overvoltage threshold (rising) X80010, X80012 Referenced to VEE X80011, X80013 Overvoltage hysteresis Undervoltage 1 hysteresis Undervoltage 1 threshold (falling) Undervoltage 2 hysteresis Undervoltage 2 threshold (falling) Drain sense voltage threshold (falling) Drain sense voltage threshold (rising) EN1 Trip Point Voltage EN2 Trip Point Voltage EN3 Trip Point Voltage EN4 Trip Point Voltage Referenced to VEE Referenced to VEE BATT-ON = VEE Referenced to VEE BATT-ON = VRGO Referenced to VEE Referenced to VEE Referenced to VEE Referenced to VEE Referenced to VEE Referenced to VEE 3.85 3.49 12 12 2.16 12 1.68 0.9 1.2 2.25 2.25 2.25 2.25 3.90 3.54 18 18 2.21 18 1.73 1 1.3 2.5 2.5 2.5 2.5 3.95 3.59 24 24 2.26 24 1.78 1.1 1.4 2.75 2.75 2.75 2.75 V mV mV V mV V V V V V V V
VOVH VUV1H VUV1F VUV2H VUV2F VDRAINF VDRAINR VTRIP1 VTRIP2 VTRIP3 VTRIP4
AC CHARACTERISTICS tFOC tFUV tFOV tVFR tBATT_ON tMRC tMRH tMRCE tMRCD tMRHE tMRHD Sense High to Gate Low Under Voltage conditions to Gate Low Overvoltage Conditions to Gate Low Overvoltage/undervoltage failure recovery time VDD does not drop below 3V, No to Gate =1V. other failure conditions. Delay BATT_ON Valid Minimum time high for reset valid on the MRC pin Minimum time high for reset valid on the MRH pin Delay from MRC enable to PWRGD HIGH Delay from MRC disable to PWRGD LOW Delay from MRH enable to Gate Pin LOW No Load Gate is On, No Load IGATE = 60A, No Load 5 5 1.0 200 1.0 1.8 1.6 1.6 400 2.4 2.6 1.5 0.5 1.0 1.2 2.5 1.0 1.5 1.6 100 3.5 1.5 2 2 s s s s ns s s s s s s
Delay from MRH disable to GATE reaching 1V IGATE = 60A, No Load
4
FN8149.0 January 13, 2005
X80010, X80011, X80012, X80013
Electrical Specifications
SYMBOL tRESET_E tQC
(Standard Settings)
TEST CONDITIONS MIN TYP MAX 1 1 85 4.5 45 85 85 100 5 50 100 100 115 5.5 55 115 115 UNIT s s ms s ms ms ms
Over the recommended operating conditions unless otherwise specified. (Continued) PARAMETER Delay from PWRGD or ViGOOD to RESET valid LOW Delay from IGQ1 and IGQ0 to valid Gate pin current
tSC_RETRY Delay between Retries tNF tDPOR tSPOR tDELAY1 tDELAY2 tDELAY3 tDELAY4 tTO ViGOOD turn off time Gate = VDD Gate = VDD Drain = VEE Drain = VEE Noise Filter for Overcurrent Device Delay before Gate assertion Delay after PWRGD and all ViGOOD signals are active before RESET assertion Power Sequencing Time Delay
TiD1 = 0; TiD0 = 0
50 1 1 1 1
ns s s s s
tPDHLPG(1) Delay from Drain good to PWRGD LOW tPDLHPG(1) Delay from Drain fail to PWRGD HIGH tPGHLPG(1) Delay from Gate good to PWRGD LOW tPGLHPG(1) Delay from Gate fail to PWRGD HIGH NOTE: 1. This parameter is based on characterization data.
Equivalent A.C. Output Load Circuit
5V 5V
4.6k RESET FAR PWRGD 30pF V1GOOD, V2GOOD, V3GOOD, V4GOOD
4.6k
30pF
A.C. Test Conditions
Input pulse levels Input rise and fall times Input and output timing levels Output load VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 Standard output load
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FN8149.0 January 13, 2005
X80010, X80011, X80012, X80013
VTH tDPOR VDD VOV VUV VUV/OV tFOV tVFR tFUV tVFR
MRH
VOCI VOC
SENSE
GATE
1V
1V
FIGURE 1. OVERVOLTAGE/UNDERVOLTAGE GATE TIMING
VTH tDPOR VDD VOCI VOC SENSE tFOC tSC_RETRY
Always Retry VUV < VUV/OV < VOV MRH = HIGH
tSC_RETRY
GATE
tFOC
FIGURE 2. OVERCURRENT GATE TIMING
Initial Power-up VDD
VTRIPi ENi tTO ViGOOD tDELAYi Enable DC/DC supply tTO
i = 1, 2, 3, 4
FIGURE 3. ViGOOD TIMINGS
6
FN8149.0 January 13, 2005
X80010, X80011, X80012, X80013
tMRH MRC tMRC
MRH
GATE
1V PWRGD tMRHE tMRHD tMRCE tMRCD
FIGURE 4. MANUAL RESET (HOT SIDE) MRH
FIGURE 5. MANUAL RESET (COLD SIDE) MRC
tDHLPG VDRAIN tDLHPG VGATE tGLHPG PWRGD tGHLPG
ENi
V1GOOD
tDELAY1
V2GOOD
tDELAY2
V3GOOD
tDELAY3
V4GOOD
tDELAY4
RESET
tSPOR
PWRGD or any ENi LOW to HIGH (1st occurance)
tRESET_E
FIGURE 6. RESET TIMINGS
7
FN8149.0 January 13, 2005
X80010, X80011, X80012, X80013 Typical Performance Characteristics
52.000 INRUSH CURRENT LIMIT (mV) 51.000 50.000 49.000 48.000 47.000 46.000 -55 -40 -25 -10 1.780 1.770 1.760 1.750 1.740 1.730 1.720 1.710 1.700 1.690 -55 -40 -25 -10 5 20 35 50 65 TEMPERATURE 80 95 110 125
Falling Rising
5
20
35
50
65
80
95
110 125
TEMPERATURE
FIGURE 7. OVER CURRENT THRESHOLD vs TEMPERATURE
UNDER VOLTAGE 2 THRESHOLD (V) ENi THRESHOLD (V)
Rising Falling
FIGURE 8. UNDERVOLTAGE 2 THRESHOLD vs TEMPERATURE
3.92 3.91 OV THRESHOLD (V) 3.90 3.89 3.88 3.87 3.86 3.85 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE
2.515 2.510 2.505 2.500 2.495 2.490 2.485 2.480 2.475 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
FIGURE 9. OVERVOLTAGE THRESHOLD vs TEMPERATURE
FIGURE 10. ENi THRESHOLD vs TEMPERATURE
UNDER VOLTAGE 1 THRESHOLD (V)
2.250 2.240 2.230
Rising
200
150A
GATE CURRENT (A)
160
120
70A 50A
2.220 2.210 2.200 2.190 -55 -40 -25 -10
Falling
80
40
10A
5
20 35 50 65 TEMPERATURE
80
95 110 125
0 -55 -40 -25 -10
5
20
35
50
65
80
95 110 125
TEMPERATURE
FIGURE 11. UNDERVOLTAGE 1 THRESHOLD vs TEMPERATURE
FIGURE 12. IGATE (SOURCE) vs TEMPERATURE
8
FN8149.0 January 13, 2005
X80010, X80011, X80012, X80013 Typical Performance Characteristics
11.0 GATE CURRENT - SINK (mA) 10.5 10.0 tOC (s) 9.5 9.0 8.5 8.0 7.5 7.0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE
(Continued)
2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 -55 -40 -25 -10
5
20
35
50
65
80
95 110 125
TEMPERATURE
FIGURE 13. IGATE (SINK) vs TEMPERATURE
FIGURE 14. TFOC vs TEMPERATURE
0.800 0.750 0.700 tUV (s) 0.650
1.02 1.00 0.98 0.96 0.94 0.92 0.90 -55
tUV2
tUV1
0.600 0.550 0.500 -55 -40 -25 -10
tDELAY (NORMALIZED)
5
20
35
50
65
80
95 110 125
-35
-15
5
25
45
65
85
TEMPERATURE
TEMPERATURE
FIGURE 15. tFUV vs TEMPERATURE
FIGURE 16. tDELAYi vs TEMPERATURE
1.4 1.4 1.3 tOV (s) 1.3 1.2 1.2 1.1 1.1 1.0 -55 -40 -25 -10
5
20
35
50
65
80
95 110 125
TEMPERATURE
FIGURE 17. tFOV vs TEMPERATURE
9
FN8149.0 January 13, 2005
X80010, X80011, X80012, X80013 Typical Performance Characteristics
52.000 INRUSH CURRENT LIMIT (mV) 51.000 50.000 49.000 48.000 47.000 46.000 -55 -40 -25 -10
(Continued)
UNDER VOLTAGE 2 THRESHOLD (V)
1.780 1.770 1.760 1.750 1.740 1.730 1.720 1.710 1.700 1.690 -55 -40 -25 -10 5 20 35 50 65 TEMPERATURE 80 95 110 125
Falling Rising
5
20
35
50
65
80
95
110 125
TEMPERATURE
FIGURE 18. OVER CURRENT THRESHOLD vs TEMPERATURE
FIGURE 19. UNDERVOLTAGE 2 THRESHOLD vs TEMPERATURE
3.92 3.91 ENi THRESHOLD (V) OV THRESHOLD (V) 3.90 3.89 3.88 3.87 3.86 3.85 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE
Falling Rising
2.515 2.510 2.505 2.500 2.495 2.490 2.485 2.480 2.475 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE
FIGURE 20. OVERVOLTAGE THRESHOLD vs TEMPERATURE
FIGURE 21. ENi THRESHOLD vs TEMPERATURE
UNDER VOLTAGE 1 THRESHOLD (V)
2.250 2.240 2.230
Rising
200
150A
GATE CURRENT (A)
160
120
70A 50A
2.220 2.210 2.200 2.190 -55 -40 -25 -10
Falling
80
40
10A
5
20 35 50 65 TEMPERATURE
80
95 110 125
0 -55 -40 -25 -10
5
20
35
50
65
80
95 110 125
TEMPERATURE
FIGURE 22. UNDERVOLTAGE 1 THRESHOLD vs TEMPERATURE
FIGURE 23. IGATE (SOURCE) vs TEMPERATURE
10
FN8149.0 January 13, 2005
X80010, X80011, X80012, X80013 Typical Performance Characteristics
11.0 GATE CURRENT - SINK (mA) 10.5 10.0 tOC (s) 9.5 9.0 8.5 8.0 7.5 7.0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE
(Continued)
2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 -55 -40 -25 -10
5
20
35
50
65
80
95 110 125
TEMPERATURE
FIGURE 24. IGATE (SINK) vs TEMPERATURE
FIGURE 25. tFOC vs TEMPERATURE
0.800 tDELAY (NORMALIZED) 0.750 0.700 tUV (s) 0.650
1.02 1.00 0.98 0.96 0.94 0.92 0.90 -55
tUV2
tUV1
0.600 0.550 0.500 -55 -40 -25 -10
5
20
35
50
65
80
95 110 125
-35
-15
5
25
45
65
85
TEMPERATURE
TEMPERATURE
FIGURE 26. tFUV vs TEMPERATURE
FIGURE 27. tDELAYi vs TEMPERATURE
1.4 1.4 1.3 tOV (s) 1.3 1.2 1.2 1.1 1.1 1.0 -55 -40 -25 -10
5
20
35
50
65
80
95 110 125
TEMPERATURE
FIGURE 28. tFOV vs TEMPERATURE
11
FN8149.0 January 13, 2005
X80010, X80011, X80012, X80013
VUV/OV
VOV Ref
PWRGD
Power Good Logic
2:1 MUX
VEE
VUV1 Ref
VUV2 Ref
BATT-ON
VEE VRGO
DRAIN
1V Ref
Over current logic, Hard short relay, Retry logic status and delay 50A
FAR
VEE
GATE IGQ1 IGQ0
Slew Rate Selection Gate Control
VDD
VDD
POR 5V reg.
VRGO RESET
VEE
VOC REF
3R 38R
Reset Logic and Delay
VEE
SENSE
VEE MRH MRC
Sequence and Timing Control logic
VEE
VRGO
OSC
Divider
Reset
4 4
V1GOOD
Select 0.1s 0.5s 1s 5s
EN1
V2GOOD
EN2 EN3 EN4
delay1 delay2 delay3 delay4
Delay circuit repeated 4 times
V3GOOD
V4GOOD
VEE
FIGURE 29. BLOCK DIAGRAM
12
FN8149.0 January 13, 2005
X80010, X80011, X80012, X80013 Pin Configuration
X80010, X80011, X80012, X80013
32-lead QFN Quad Package
PWRGD BATT-ON MRH IGQ0 IGQ1 FAR NC VEE
VRGO NA1 V4GOOD EN4 V3GOOD EN3 V2GOOD EN2
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25
24 23 22 21 20 19 18 17
NC MRC NA1 RESET V1GOOD EN1 NA2 NA2
(7mm x 7mm)
9 10 11 12 13 14 15 16
VUV/OV
VDD
VEE
SENSE
DRAIN
GATE
NA1
Pin Descriptions
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME VRGO NA1 V4GOOD EN4 V3GOOD EN3 V2GOOD EN2 VDD VEE VUV/OV SENSE GATE DRAIN NA1 NA1 NA2 NA2 EN1 V1GOOD DESCRIPTION Regulated 5V output. Used to pull-up user programmable inputs IGQ0, IGQ1, BATT-ON (if needed). Not Available. Do not connect to this pin. V4 Voltage Good Output. This open drain output goes LOW when EN4 is less than VTRIP4 and goes HIGH when EN4 is greater than VTRIP4. There is a user selectable delay circuitry on this pin. V4 Voltage Enable Input. Fourth voltage enable pin. If unused connect to VRGO. V3 Voltage Good Output (Active Low). This open drain output goes LOW when EN3 is less than VTRIP3 and goes HIGH when EN3 is greater than VTRIP3. There is a user selectable delay circuitry on this pin. V3 Voltage Enable Input. Third voltage enable pin. If unused connect to VRGO. V2 Voltage Good Output (Active Low). This open drain output goes LOW when EN2 is less than VTRIP2 and goes HIGH when EN2 is greater than VTRIP2. There is a user selectable delay circuitry on this pin. V2 Voltage Enable Input. Second voltage enable pin. If unused connect to VRGO. Positive Supply Voltage Input. Negative Supply Voltage Input. Analog Undervoltage and Overvoltage Input. Turns off the external N-channel MOSFET when there is an undervoltage or overvoltage condition. Circuit Breaker Sense Input. This input pin detects the overcurrent condition. Gate Drive Output. Gate drive output for the external N-channel MOSFET. Drain. Drain sense input of the external N-channel MOSFET. Not Available. Do not connect to this pin. Not Available. Do not connect to this pin. Not Available. Connect to VRGO. Not Available. Connect to VRGO. V1 Voltage Enable Input. First voltage enable pin. If unused connect to VRGO. V1 Voltage Good Output (Active Low).This open drain output goes LOW when EN1 is less than VTRIP1 and goes HIGH when EN1 is greater than VTRIP1. There is a user selectable delay circuitry on this pin.
13
NA1
FN8149.0 January 13, 2005
X80010, X80011, X80012, X80013 Pin Descriptions
PIN 21 22 23 24 25 26 27 28 29 30 31 32 NAME RESET NA1 MRC NC VEE NC FAR BATT-ON PWRGD IGQ1 IGQ0 MRH (Continued) DESCRIPTION RESET Output. This open drain pin is an active LOW output. This pin will be active until PWRGD goes active and the power sequencing is complete. This pin will be released after a programmable delay. Not Available. Do not connect to this pin. Manual Reset Input Cold-side. Pulling the MRC pin HIGH initiates a system side RESET. The MRC signal must be held HIGH for 5s. It has an internal pulldown resistor. (>10m typical) No Connect. No internal connections. Negative Supply Voltage Input. No Connect. No internal connections. Failure After Re-try (FAR) output signal. Failure After Re-try (FAR) is asserted after a number of retries. Used for Overcurrent and hardshort detection. Battery On Input. This input signals that the battery backup (or secondary supply) is supplying power to the backplane. It has an internal pulldown resistor. (>10m typical) Power Good Output. This output pin enables a power module. Gate Current Quick Select Bit 1 Input. This pin is used to change the gate current drive and is intended to allow for current ramp rate control of the gate pin of an external FET. It has an internal pulldown resistor. (>10m typical) Gate Current Quick Select Bit 0 Input. This pin is used to change the gate current drive and is intended to allow for current ramp rate control of the gate pin of an external FET. It has an internal pulldown resistor. (>10m typical) Manual Reset Input Hot-side. Pulling the MRH pin LOW initiates a GATE pin reset (GATE pin pulled LOW). The MRH signal must be held LOW for 5s (minimum).
Functional Description
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the bypass capacitors at the input of the board's power module or DC/DC converter can draw huge transient currents as they charge up (See Figure 30). This transient current can cause permanent damage to the board's components and cause transients on the system power supply.
(DC/DC converter) off until the backplane input voltage is stable and within tolerance.
-48V Return R4 182K 1%
R5 30k 1%
UV=37V VUV/OV OV=71V VDD
X80010 X80011 X80012 X80013
DRAIN
DC/DC Converter
R6 10K 1%
VEE SENSE 0.1F
DC/DC Converter
GATE
Rs 0.02 5%
4.7k 100 3.3n
100K
FIGURE 31. TYPICAL INRUSH WITH GATE SLEW RATE CONTROL
-48V
-48V
Iinrush
Q1 IRFR120
Overvoltage and Undervoltage Shutdown
The X80010 provides overvoltage and undervoltage protection circuits. When an overvoltage (VOV) or undervoltage (VUV1 and VUV2) condition is detected, the GATE pin immediately pulls low. The undervoltage threshold VUV1 applies to the normal operation with a mains supply. The undervoltage threshold VUV2 assumes the system is powered by a battery. When using a battery backup, the
FN8149.0 January 13, 2005
FIGURE 30. TYPICAL -48V HOTSWAP APPLICATION CIRCUIT
The X80010 is designed to turn on a board's supply voltage in a controlled manner (see Figure 31), allowing the board to be safely inserted or removed from a live backplane. The device also provides undervoltage, overvoltage and overcurrent protection while keeping the power module 14
X80010, X80011, X80012, X80013
BATT-ON pin is pulled to VRGO. The default thresholds have been set so the external resistance values in Figure 30 provide an overvoltage threshold of 74.9V (X80010/X80012) or 68V (X80011/X80013), a main undervoltage threshold of 43V and a battery undervoltage threshold of 33.8V. As shown in Figure 34, this circuit block contains comparators and voltage references to monitor for a single overvoltage and dual undervoltage trip points. The overvoltage and undervoltage trip points as shown in Table 1.
TABLE 1. OVERVOLTAGE/UNDERVOLTAGE DEFAULT THRESHOLDS THRESHOLD SYMBOL VOV VOV VUV1 VUV2 DESCRIPTION Overvoltage (X80010/12) Overvoltage (X80011/13) Undervoltage 1 Undervoltage 2 MAX/MIN LOCKOUT FALLING RISING VOLTAGE1 VOLTAGE2 3.87V 3.51V 2.21V 1.73V 3.9V 3.54V 2.24V 1.76V 74.3 67.4 43.0 33.8 74.9 68 42.4 33.2
OPERATING VOLTAGE (V)
100 90 80 70 60 50 40 30 20 10 150 0
VOV VUV1 VUV2
158 166 175 182 190 198 BATT-ON = VEE
Operating Voltage
BATT-ON = VRGO
206
214
R1 in k (for R2=10K)
FIGURE 33. OPERATING VOLTAGe vs RESISTOR RATIO
Battery Back Up Operations
An external signal, BATT_ON is provided to switch the undervoltage trip point. The BATT_ON signal is a LOGIC HIGH if VIHB > VEE + 4V and is a LOGIC LOW if VILB < VEE + 2V. The time from a BATT_ON input change to a valid new undervoltage threshold is 100ns. See Electrical Specifications for more details. Note: The VUV/OV pin must be limited to less than VEE + 5.5V in worst case conditions. Values for R1 and R2 must be chosen such that this condition is met. Intersil recommends R1 = 182k and R2 = 10k to conform to factory settings.
TABLE 2. SELECTING BETWEEN UNDERVOLTAGE TRIP POINTS PIN BATT_ON DESCRIPTION Undervoltage Trip Point Selection Pin TRIP POINT SELECTION If BATT_ON = 0, VUV1 trip point is selected; If BATT_ON = 1, VUV2 trip point is selected.
Notes: 1: Max/Min Voltage is the maximum and minimum operating voltage assuming the recommended VUV/OV resistor divider. 2: Lockout voltage is the voltage where the X8001x turns off the FET.
A resistor divider connected between the plus and minus input voltages and the VUV/OV pin (see Figure 32) determines the overvoltage and undervoltage shutdown voltages and the operating voltage range. Using the thresholds in Table and the equations of Figure 32 the desired operating voltage can be determined. Figure 33 shows the resistance values for various operating voltages (X80010 and X80012).
VP R1 VS VUV/OV
VUV1 and VUV2 are undervoltage thresholds.
Voltage divider:
R2 V UV OV = V S --------------------- R1 + R2
R1 182K VUV/OV R2 10K -48V + VUV1 + VUV2 BATT_ON Voltage Reference Voltage Reference 2:1 Mux + VOV Voltage Reference
or:
R1 + R2 V S = V UV OV --------------------- R2
To Gate Control
R2 VN
To Gate Control
FIGURE 32. OVERVOLTAGE UNDERVOLTAGE DIVIDER
FIGURE 34. OVERVOLTAGE UNDERVOLTAGE FOR PRIMARY AND BATTERY BACKUP
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X80010, X80011, X80012, X80013
Overcurrent Protection (Circuit Breaker Function)
The X80010 over-current circuit provides the following functions: - Over-current shut-down of the power FET and external power good indicators. - Noise filtering of the current monitor input. - Relaxed over-current limits for initial board insertion. - Over-current recovery retry operation. A sense resistor, placed in the supply path between VEE and SENSE (see Figure 30) generates a voltage internal to the X80010. When this voltage exceeds 50mV an over current condition exists and an internal "circuit breaker" trips, turning off the gate drive to the external FET. The actual overcurrent level is dependent on the value of the current sense resistor. For example a 20m sense resistor sets the overcurrent level to 2.5A. Intersil's X80010 provides a safety mechanism during insertion of the board into the back plane. During insertion of the board into the backplane large currents may be induced. In order to prevent premature shut down, the overcurrent detect circuit of the X80010 allows up to 3 times the standard overcurrent setting during insertion. After the PWRGD signal is asserted, the X80010 switches back to the normal overcurrent setting. The over-current threshold voltage during insertion is 150mV. After the Power FET turns off due to an over-current condition, a retry circuit turns the FET back on after a delay of 100ms. If the over-current condition remains, the FET again turns off. For the X80010 and X80012, this sequence repeats indefinitely until the over-current condition is released. For the X80011 and X80013, the X80010 retries five times, then, sets an output signal, FAR, to indicate a failure after retry.
Voltage Reference Gate Control Block - 3R + 5s noise filtering
38R Overcurrent/ Short-Circuit Retry Logic RETRY Delay
-48V RSense Overcurrent Event
FIGURE 35. OVERCURRENT DETECTION/SHORT CIRCUIT PROTECTION
The overcurrent voltage threshold (VOC) is 50mV. This can be factory set, by special order, to any setting between 30mV and 100mV. VOC is the voltage between the SENSE and VEE pins and across the RSENSE resistor. If the selected sense resistor is 20mW, then 50mV corresponds to an overcurrent of 2.5A. If an over-current condition is detected, the GATE is turned off and all power good indicators go inactive.
Overcurrent Noise Filter
The X80010 has a noise (low pass) filter built into the overcurrent comparator. The comparator will thus require the current spikes to exceed the overcurrent limit for more than 5s.
Overcurrent During Insertion
Insertion is defined as the first plug-in of the board to the backplane. In this case, the X80010 is initially fully powered off prior to the hot plug connection to the mains supply. This condition is different from a situation where the mains supply has temporarily failed resulting in a partial recycle of the power. This second condition will be referred to as a power cycle. During insertion, the board can experience high levels of current for short periods of time as power supply capacitors charge up on the power bus. To prevent the over-current sensor from turning off the FET inadvertently, the X80010 has the ability to allow more current to flow through the powerFET and the sense resistor for a short period of time until the FET turns on and the PWRGD signal goes active. In the X80010, 150mV is allowed across sense resistor the during insertion (10A assuming a 20m resistor). This provides a mechanism to reduce insertion issues associated with huge current surges.
Over-current shut-down
As shown in Figure 35, this circuit block contains a resistor divider, a comparator, a noise filter and a voltage reference to monitor for over-current conditions.
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Hardshort Protection - FET Turn-on Retry
In the event on an over-current or hard short condition, the X80010 includes a retry circuit. This circuit waits for 100ms, then attempts to again turn on the FET. If the fault condition still exists, the FET turns off and the sequence repeats. For the X80010 and X80012, this process continues indefinitely until the overcurrent condition does not exist. For the X80011 and X80013, this process repeats five times, only then will keep the FET off and set the FAR pin active. After FAR is asserted, it can be cleared using the master reset pin, MRH (upon MRH assertion the FAR output is cleared) or cycling the power on VDD. If an overcurrent condition does not occur on any retry, the gate pin proceeds to open at the user defined slew rate. For applications that require different ramp rates during insertion and operation or for applications where a different gate current is desired, the X80010 provides two external pins, IGQ1 and IGQ0, that allow the system to switch to a different GATE current with pre-selected options. The IGQ1 and IGQ0 pins can be used to select from one of four set values.
IGQ1 PIN 0 0 1 1 IGQ0 PIN 0 1 0 1 CONTENTS Defaults to gate current 50A Gate Current is 10A Gate Current is 70A Gate Current is 150A
Gate Drive Output Slew Rate (Inrush Current) Control
The gate output drives an external N-Channel FET. The GATE pin goes high when no overcurrent, undervoltage or overvoltage conditions exist. The X80010 provides an IGATE current of 50A to provide on-chip slew rate control to minimize inrush current. This IGATE current limits the inrush current and provides the best charge time for a given load, while avoiding overcurrent conditions. For applications that require different ramp rates during insertion and start-up and operations modes, the X80010 provides two external pins, IGQ1 and IGQ0, that allow the user to switch to different GATE currents on-the-fly by selecting one of four pre-selected IGATE currents. When IGQ0 and IGQ1 are left unconnected, the gate current is 50A. The other three settings are 10A, 70A and 150A (See Figure 36). Typically, the delay from IGQ1 and IGQ0 selection to a change in the GATE pin current is less than 1s.
IGATE =150A overcurrent 70A 50A 10A IGATE
Typically, the delay from IGQ1 and IGQ0 selection to a change in the GATE pin current is less than 1s.
Gate Current Quick Select Logic
VDD=12V 10A 50A 70A 150A Slew Rate Selection Logic
IGQ1 IGQ0
Control Registers
VEE
SENSE GATE
DRAIN
100nF*
R2 100* 22K
C2 3.3nF
100K
-48V RSENSE IINRUSH
LOAD * Optional Components See Section "Gate Capacitor, Filtering and Feedback"
FIGURE 37. SLEW RATE (INRUSH CURRENT) CONTROL
Gate Capacitor, Filtering and Feedback
In Figure 37, the FET control circuit includes an FET feedback capacitor C2, which provides compensation for the FET during turn on. The capacitor value depends on the load, the FET gate current, and the maximum desired inrush current. The value of C2 can be selected with the following formula.
Inrush Current
T1
T2 T3 Time, ms
T4
T5
FIGURE 36. SELECTING IGATE CURRENT FOR SLEW RATE CONTROL ON THE GATE PIN
I GATE x C LOAD C2 = -----------------------------------------I INRUSH
Where:
Slew Rate (Gate) Control
As shown in Figure 37, this circuit block contains a current source (IGATE) that drives the 50A current into the GATE pin. This current provides a controlled slew rate for the FET.
IGATE = FET Gate current IINRUSH = Maximum desired inrush current CLOAD = DC/DC bulk capacitance
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X80010, X80011, X80012, X80013
With the X80010, there is some control of the gate current with the IGQ pins, so one selection of C2 can cover a wide range of possible loading conditions. Typical values for C2 range from 2.2 to 4.7nF. When power is applied to the system, the FET tries to turn on due to its internal gate to drain capacitance (Cgd) and the feedback capacitor C2 (see Figure 37.) The X80010 device, when powered, pulls the gate output low to prevent the gate voltage from rising and keep the FET from turning on. However, unless VDD powers up very quickly, there will be a brief period of time during initial application of power when the X80010 circuits cannot hold the gate low. The use of an external capacitor (C1) prevents this. Capacitors C1 and C2 form a voltage divider to prevent the gate voltage from rising above the FET turn on threshold before the X80010 can hold the gate low. Use the following formula for choosing C1.
V1 - V2 C1 = -------------------- C2 V2
The PWRGD signal asserts (Logic LOW) only when all of the below conditions are true: - there is no overvoltage or no undervoltage condition, (i.e. undervoltage < VEE < overvoltage.) - There is no overcurrent condition (i.e. VEE - VSENSE < VOC.) - The FET is turned on (i.e. VDRAIN < VEE + 1V and VGATE > VDD - 1V).
PWRGD
- +
VDRAIN
Power Good Logic
VEE
1V (Factory Programmable)
Control/Status Registers
- +
VGATE
VDD-1V
Where: V1 = Maximum input voltage, V2 = FET threshold voltage, C1 = Gate capacitor, C2 = Feedback capacitor. In a system where VDD rises very fast, a smaller value of C1 may suffice as the X80010 will control voltage at the gate before the voltage can rise to the FET turn on threshold. The circuit of Figure 37 assumes that the input voltage can rise to 80V before the X80010 sees operational voltage on VDD. If C1 is used then the series resistor R1 will be required to prevent high frequency oscillations.
-48V VEE
SENSE GATE
DRAIN 100K
LOAD RSENSE
FIGURE 38. DRAIN SENSE AND POWER GOOD INDICATOR
Power On/System Reset and Delay
Application of power to the X80010 activates a Power On Reset circuit that pulls the RESET pin active. This signal, if used, provides several benefits. - It prevents the system microprocessor from starting to operate with insufficient voltage. - It prevents the processor from operating prior to stabilization of the oscillator. - It allows time for an FPGA to download its configuration prior to initialization of the circuit. The POR/RESET circuit is activated when all voltages are within specified ranges and the following time-out conditions are met: PWRGD and V1GOOD, V2GOOD, V3GOOD, and V4GOOD. The POR/RESET circuit will then wait 100ms and assert the RESET pin.
Drain Sense and Power Good Indicator
The X80010 provides a drain sense and power good indicator circuit. The PWRGD signal asserts LOW when there is no overvoltage, no undervoltage, and no overcurrent condition, the Gate voltage exceeds VDD-1V, and the voltage at the DRAIN pin is less VEE+VDRAIN. As shown in Figure 38, this circuit block contains a drain sense voltage trip point (VDRAIN) and a gate voltage trip point (VGATE), two comparators, and internal voltage references. These provide both a drain sense and a gate sense circuit to determine the whether the FET has turned on as requested. If so, the power good indicator (PWRGD) goes active. The drain sense circuit checks the DRAIN pin. If the voltage on this pin is greater that 1V above VEE, then a fault condition exists. The gate sense circuit checks the GATE pin. If the voltage on this pin is less than VEE - 1V, then a fault condition exists.
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Once the PWRGD signal is asserted, the power sequencing of the DC/DC modules can commence. RESET goes active 100ms after all ViGOOD (i=1 to 4) outputs are asserted (See Figure 39).
PWRGD
Drain Sense & Power Good Logic Enable Logic ViGOOD i = 1 to 4 SPOR RESET RESET Logic tSPOR Delay
VEE
As shown in Figure 40, this circuit block contains four separate voltage enable pins, a time delay circuit, and an output driver.
VDD
P
MRC Control Registers
FIGURE 39. POWER ON/SYSTEM RESET AND DELAY
Quad Voltage Monitoring
X80010 monitors 4 voltage enable inputs. When the ENi (i=1-4) input is detected to be below the input threshold, the output ViGOOD (i = 1 to 4) goes active LOW. The ViGOOD signal is asserted after a delay of 100ms. The ViGOOD signal remains active until ENi rises above threshold.
VRGO
OSC
Divider
Reset
Control Register
4
4
V1GOOD
Select 0.1s 0.5s 1s 5s
EN1
V2GOOD
EN2 EN3 EN4
delay1 delay2 delay3 delay4
Delay circuit repeated 4 times
V3GOOD
V4GOOD
VEE
FIGURE 40. VOLTAGE MONITORS AND VGOOD OUTPUTS
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Manual Reset (Hot Side and Cold Side)
The manual reset option allows a hardware reset of either the Gate control or the PWRGD indicator. These can be used to recover the system in the event of an abnormal operating condition.The X80010 has two manual reset pins: MRH (manual reset hot side) and MRC (manual reset cold side). The MRH signal is used as a manual reset for the GATE pin. This pin is used to initiate Soft Reinsert. When MRH is pulled LOW the GATE pin will be pulled LOW. It also clears the FAR signal. When the MRH pin goes HIGH, it removes the override signal and the gate will turn on based on the selected gate control mechanism.
TABLE 3. MANUAL RESET OF THE HOT SIDE (GATE SIGNAL) MRH 1 0 GATE PIN Operational OFF REQUIREMENTS When MRH is HIGH the Manual Reset (Hot) function is disabled MRH must be held LOW minimum of 5s
The MRC signal is used as a manual reset for the PWRGD signal. This pin is used to initiate a Soft Restart. When the MRC is pulled HIGH, the PWRGD signal is pulled HIGH. When MRC pin goes LOW, the PWRGD pin goes operational. It will go LOW if all constraints on the GATE are within limits.
TABLE 4. MANUAL RESET OF THE COLD SIDE (PWRGD SIGNAL) MRC 1 0 PWRGD HIGH Operational REQUIREMENTS MRC must be held HIGH minimum of 5s When MRC is LOW the MRC function is disabled
Flexible Power Sequencing of Multiple Power Supplies
The X80010 provides several circuits such as multiple voltage enable pins, programmable delays, and a power good signals can be used to set up flexible power sequencing schemes for downstream DC/DC supplies. Below are examples of parallel and relay sequencing. 1. Power Up of DC/DC Supplies In Parallel Sequencing Using Programmable Delays on Power Good (See Figure 41 and Figure 42). Several DC/DC power supplies and their respective power up start times can be controlled using the X80010 such that each of the DC/DC power supplies will start up following the issue of the PWRGD signal. The PWRGD signal is fed into the ENi inputs to the X80010. When PWRGD is valid, the internal voltage enable circuits issue ViGOOD signals after a time delay. The ViGOOD signals control the ON/OFF pins of the DC/DC supplies. Each DC/DC converter is instructed to turn on 100ms after the PWRGD goes active. However, each ViGOOD delay can be increased with the use of external R-C circuits.
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X80010, X80011, X80012, X80013
-48V Return
MRH R4 182k 1%
MRC
V4GOOD EN4 V3GOOD EN3
UV=37V VUV/OV OV=71V VDD
R5 30k 1%
X80010, X80011, X80013, X80014
V2GOOD EN2 V1GOOD EN1
R6 10k 1%
VEE
SENSE
0.1F
GATE
4.7K
DRAIN RESET PWRGD 100K OPTO COUPLER OPTO COUPLER PWRGD
100
Rs
3.3n
-48V
0.02 5%
Q1 IRFR120
RESET `
ON/OFF 9 VIN+ VOUT+ SENSE+ 8 7 TRIM VINRESET VCC1 VCC2 C
GND
C3 0.1F 100V + C4 100F 100V
1
3.3V
+
4
6 SENSEVOUT 5
C5 100F 16V
GND
C6 0.1F 100V + C7 100F 100V
1
ON/OFF 9 VIN+ VOUT+ SENSE+ 8 7 TRIM VINSENSEVOUT 5
2.5V
+ C8 100F 16V
VCC1 VCC2 FPGA
6
4
GND
C9 0.1F 100V + C10 100F 100V
1
ON/OFF 9 VIN+ VOUT+ SENSE+ 8 7 TRIM VINSENSEVOUT 5
1.8V
+
6
C11 100F 16V
VCC1
VCC2
4
ASIC
GND
C12 0.1F 100V + C13 100F 100V
1
ON/OFF 9 VIN+ VOUT+ SENSE+ 8 7 TRIM VINSENSEVOUT 5
1.2V
+ C14 100F 16V
6
4
FIGURE 41. TYPICAL APPLICATION OF HOTSWAP AND DC/DC PARALLEL POWER SEQUENCING
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the X80010 EN1 input to sequence the next supply. An opto-coupler is recommended in this connection for isolation. This configuration ensures that each subsequent DC/DC supply will power up after the preceding DC/DC supply voltage output is valid.
100ms Power Supply #1 turns ON
Main FET turns ON EN1 (from PWRGD)
tDELAY1
V1GDO Power Supply #1 OUTPUT (3.3V) EN2 (from PWRGD)
tDELAY2
100ms Power Supply #2 turns ON
V2GDO Power Supply #2 OUTPUT (2.5V)
EN3 (from PWRGD)
tDELAY3
100ms Power Supply #3 turns ON
V3GDO Power Supply #3 OUTPUT (1.8V) EN4 (from PWRGD)
tDELAY4
100ms Power Supply #4 turns ON
V4GDO Power Supply #4 OUTPUT (1.2V)
tSPOR
100ms
RESET
All ViGOOD=LOW
FIGURE 42. PARALLEL SEQUENCING OF DC/DC SUPPLIES. (TIMING)
1. Power Up of DC/DC Supplies Via Relay Sequencing Using Power Good and Voltage Monitors (see Figure 43 and Figure 44). Several DC/DC power supplies and their respective power up start times can be controlled using the X80010 such that each of the DC/DC power supplies will start in a relay sequencing fashion. The 1st DC/DC supply will power up when PWRGD is LOW after a 100ms delay. Subsequent DC/DC supplies will power up after the prior supply has reached its operating voltage. One way to do this is by using an external CPU Supervisor (for example the Intersil X40430) to monitor the DC/DC output. When the DC/DC voltage is good, the supervisor output signals 22
FN8149.0 January 13, 2005
X80010, X80011, X80012, X80013
UV=37V VUV/OV OV=71V VDD
R5 30k 1%
X80010, X80011, X80012, X80013
V2GOOD EN2 V1GOOD EN1
OPTO COUPLER
VFAIL<1:3>
-48V Return
MRH R4 182k 1%
MRC
OPTO COUPLER
V4GOOD EN4 V3GOOD EN3
X40430
R6 10k 1%
VEE
SENSE
0.1F 100
GATE
4.7K
DRAIN RESET PWRGD
VMON<1:3>
Rs
3.3n 100K
OPTO COUPLER PWRGD RESET
-48V
0.02 5%
Q1 IRFR120
GND
C3 0.1F 100V + C4 100F 100V
1
ON/OFF 9 VIN+ VOUT+ SENSE+ 8 7 TRIM VIN-
3.3V
+
RESET VCC1 VCC2 C
4
6 SENSEVOUT 5
C5 100F 16V
GND
C6 0.1F 100V + C7 100F 100V
1
ON/OFF 9 VIN+ VOUT+ SENSE+ 8 7 TRIM VINSENSEVOUT 5
2.5V
+
VCC1 VCC2 FPGA
6
C8 100F 16V
4
GND
C9 0.1F 100V + C10 100F 100V
1
ON/OFF 9 VIN+ VOUT+ SENSE+ 8 7 TRIM VINSENSEVOUT 5
1.8V
+ C11 100F 16V
VCC1
VCC2
6
4
ASIC
GND
C12 0.1F 100V + C13 100F 100V
1
ON/OFF 9 VIN+ VOUT+ SENSE+ 8 7 TRIM VINSENSEVOUT 5
1.2V
+
6
C14 100F 16V
4
FIGURE 43. TYPICAL APPLICATION OF HOTSWAP AND DC/DC RELAY SEQUENCING
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FET turns ON EN2 In (from PWRGD)
tDELAY1
100ms Power Supply #1 turns ON V2MON threshold
V1GDO Power Supply #1 OUTPUT (3.3V) EN2
tDELAY2
100ms Power Supply #2 turns ON V3MON threshold
V2GDO Power Supply #2 OUTPUT (2.5V) EN3
tDELAY3
100ms Power Supply #3 turns ON V4MON threshold
V3GDO Power Supply #3 OUTPUT (1.8V) EN4
tDELAY4
100ms Power Supply #4 turns ON
V4GDO Power Supply #4 OUTPUT (1.2V)
tRESET
100ms
RESET FIGURE 44. RELAY SEQUENCING OF DC/DC SUPPLIES. (TIMING)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 24
FN8149.0 January 13, 2005
X80010, X80011, X80012, X80013 Packaging Information
32-Lead Very Very Thin Quad Flat No Lead Package 7mm x 7mm Body with 0.65mm Lead Pitch
0.007 (0.19) 0.009 (0.25) 0.000 (0.00) 0.002 (0.05)
0.009 (0.23) 0.015 (0.38)
0.185 (4.70)
0.271 (6.90) 0.279 (7.10)
0.000 (0.00) 0.030 (0.76) 0.185 (4.70) PIN 1 INDENT
0.027 (0.70) 0.031 (0.80)
0.014 (0.35) 0.029 (0.75)
0.271 (6.90) 0.279 (7.10)
0.271 (6.90) 0.279 (7.10)
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FN8149.0 January 13, 2005

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